Invention Publication
- Patent Title: SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS
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Application No.: US18410917Application Date: 2024-01-11
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Publication No.: US20240145477A1Publication Date: 2024-05-02
- Inventor: Sairam SUBRAMANIAN , Walid M. HAFEZ
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/768 ; H01L21/8238 ; H01L29/66 ; H01L29/78

Abstract:
Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.
Public/Granted literature
- US12199101B2 Self-aligned gate endcap (SAGE) architecture having gate contacts Public/Granted day:2025-01-14
Information query
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