公开(公告)号：US20240006254A1

公开(公告)日：2024-01-04

申请号：US17855636

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Xiao WEN ,  Dipto THAKURTA ,  Sairam SUBRAMANIAN

IPC: H01L21/66 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L22/34 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments described herein may be related to apparatuses, systems, processes, and/or techniques for identifying device defects on a wafer substrate using voltage contrast techniques and electronic beam scans by scanning an area on a portion of the wafer that includes ends of a plurality of traces that extend from the scan area respectively to blocks on the wafer that include devices to be tested. During the electronic beam scan, ends of the plurality of traces within the scan area that are coupled with devices that are electrically shorted will appear bright, and those that are electrically open will appear dark. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093588A1

公开(公告)日：2022-03-24

申请号：US17026040

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Chia-Hong JAN ,  Tanuj TRIVEDI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

Abstract: Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.

公开(公告)号：US20240145477A1

公开(公告)日：2024-05-02

申请号：US18410917

申请日：2024-01-11

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

公开(公告)号：US20220393013A1

公开(公告)日：2022-12-08

申请号：US17339146

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sairam SUBRAMANIAN ,  Conor P. PULS ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.

公开(公告)号：US20220077302A1

公开(公告)日：2022-03-10

申请号：US17526986

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US20210305243A1

公开(公告)日：2021-09-30

申请号：US16830120

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Chia-Hong JAN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.

公开(公告)号：US20240329122A1

公开(公告)日：2024-10-03

申请号：US18128617

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Amit PALIWAL ,  Xiao WEN ,  Dipto THAKURTA

IPC: G01R31/28

CPC classification number: G01R31/2884

Abstract: A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

公开(公告)号：US20220077145A1

公开(公告)日：2022-03-10

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20200286891A1

公开(公告)日：2020-09-10

申请号：US16294380

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Kiran CHIKKADI

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00 ,  H01L23/528

Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.

公开(公告)号：US20200286890A1

公开(公告)日：2020-09-10

申请号：US16294210

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.