Invention Publication
- Patent Title: VERA DETECTION METHOD TO CATCH ERASE FAIL
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Application No.: US18356786Application Date: 2023-07-21
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Publication No.: US20240161858A1Publication Date: 2024-05-16
- Inventor: Parth Amin , Sai Gautham Thoppa , Anubhav Khandelwal
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Main IPC: G11C29/46
- IPC: G11C29/46 ; G11C16/14 ; G11C29/12

Abstract:
Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.
Public/Granted literature
- US12272417B2 Vera detection method to catch erase fail Public/Granted day:2025-04-08
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