Invention Publication
- Patent Title: FLIP-FLOP BASED ON CLOCK SIGNAL AND PULSE SIGNAL
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Application No.: US18507867Application Date: 2023-11-13
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Publication No.: US20240162893A1Publication Date: 2024-05-16
- Inventor: HYUNCHUL HWANG , JEONGJIN LEE , SEUNGMAN LIM
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR SUWON-SI
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR SUWON-SI
- Priority: KR 20220152003 2022.11.14 KR 20230055654 2023.04.27
- Main IPC: H03K3/037
- IPC: H03K3/037 ; H03K3/012

Abstract:
A flip-flop (FF) includes a first n-channel metal oxide semiconductor (NMOS) transistor connected to a ground line, a first p-channel metal oxide semiconductor (PMOS) transistor connected to a power voltage line, a second NMOS transistor connecting a first node to the first NMOS transistor, a second PMOS transistor connecting the first node to the first PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, connected to the second NMOS transistor in parallel, and forming a first discharge path for connecting the first node to the ground line, a third PMOS transistor and a fourth PMOS transistor, connected to the second PMOS transistor in parallel, and forming a first charge path for connecting the first node to the power voltage line, a keeper circuit connected to the first node to maintain a voltage level of the first node.
Information query
IPC分类: