公开(公告)号：US20240162893A1

公开(公告)日：2024-05-16

申请号：US18507867

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNCHUL HWANG ,  JEONGJIN LEE ,  SEUNGMAN LIM

IPC: H03K3/037 ,  H03K3/012

CPC classification number: H03K3/037 ,  H03K3/012

Abstract: A flip-flop (FF) includes a first n-channel metal oxide semiconductor (NMOS) transistor connected to a ground line, a first p-channel metal oxide semiconductor (PMOS) transistor connected to a power voltage line, a second NMOS transistor connecting a first node to the first NMOS transistor, a second PMOS transistor connecting the first node to the first PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, connected to the second NMOS transistor in parallel, and forming a first discharge path for connecting the first node to the ground line, a third PMOS transistor and a fourth PMOS transistor, connected to the second PMOS transistor in parallel, and forming a first charge path for connecting the first node to the power voltage line, a keeper circuit connected to the first node to maintain a voltage level of the first node.

公开(公告)号：US20160071255A1

公开(公告)日：2016-03-10

申请号：US14940880

申请日：2015-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGJIN LEE ,  Chan Hwang ,  Seungyoon Lee

IPC: G06T7/00 ,  H04N5/33 ,  H04N5/225

CPC classification number: G06T7/001 ,  G03F7/70633 ,  G06T7/174 ,  G06T2207/10048 ,  G06T2207/10152 ,  G06T2207/30148 ,  G06T2207/30204 ,  H04N5/2256 ,  H04N5/332

Abstract: A method for measuring overlay includes receiving a first image of a first overlay mark captured using light having a first wavelength. The method includes receiving a second image of a second overlay mark captured using light having a second wavelength different from the first wavelength. The method includes measuring a displacement between a central portion of the first image and a central portion of the second image, wherein the first and second overlay marks are disposed on different levels.

Abstract translation: 一种用于测量覆盖层的方法包括接收使用具有第一波长的光捕获的第一覆盖标记的第一图像。 该方法包括接收使用具有不同于第一波长的第二波长的光捕获的第二重叠标记的第二图像。 该方法包括测量第一图像的中心部分和第二图像的中心部分之间的位移，其中第一和第二覆盖标记设置在不同的水平上。

公开(公告)号：US20230207595A1

公开(公告)日：2023-06-29

申请号：US18055069

申请日：2022-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGYONG UM ,  JEONGJIN LEE

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14689

Abstract: An image sensor includes a semiconductor substrate including a first pixel group and a second pixel group, each of which includes at least four pixel regions, the first and second pixel groups sharing a first pixel region of the pixel regions, a pixel isolation structure disposed in the semiconductor substrate and surrounding each of the pixel regions, a first device isolation pattern provided in the second pixel group and disposed on a first portion of the pixel isolation structure, a floating diffusion region disposed adjacent to the first device isolation pattern in each of the pixel regions, a ground dopant region provided in the first pixel group and disposed on a second portion of the pixel isolation structure, and a second device isolation pattern provided in the first pixel group and disposed between the second portion of the pixel isolation structure and the ground dopant region.

公开(公告)号：US20210143800A1

公开(公告)日：2021-05-13

申请号：US16891521

申请日：2020-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGJIN LEE ,  MINSU KIM ,  AHREUM KIM

IPC: H03K3/012 ,  H03K3/3562 ,  H01L27/092 ,  G06F30/3953 ,  G06F30/398 ,  G06F30/392

Abstract: The present disclosure relates to a hybrid standard cell that includes a semiconductor substrate, a first power rail, a second power rail, a high-speed transistor region and a low-power transistor region. The first power rail and the second power rail are formed above the semiconductor substrate and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The high-speed transistor region and the low-power transistor region are adjacent to each other in the first direction and arranged in a row region between the first power rail and the second power rail. An operation speed of a high-speed transistor formed in the high-speed transistor region is higher than an operation speed of a low-power transistor formed in the low-power transistor region, and a power consumption of the high-speed transistor is lower than a power consumption of the high-speed transistor.