Invention Publication
- Patent Title: POWER EFFICIENT DISPLAY ARCHITECTURE
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Application No.: US18056649Application Date: 2022-11-17
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Publication No.: US20240169883A1Publication Date: 2024-05-23
- Inventor: Chun WANG , Sreekanth MODAIKKAL , Kumar SAURABH , Samson KIM , Kit Fong NG
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Main IPC: G09G3/20
- IPC: G09G3/20 ; G09G3/00 ; G09G5/391

Abstract:
This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.
Public/Granted literature
- US12100335B2 Power efficient display architecture Public/Granted day:2024-09-24
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