Invention Publication
- Patent Title: BIT FLIPPING DECODER WITH OPTIMIZED MAXIMUM ITERATIONS FOR VARIED BIT FLIPPING THRESHOLDS
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Application No.: US18521574Application Date: 2023-11-28
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Publication No.: US20240176509A1Publication Date: 2024-05-30
- Inventor: Mustafa N. Kaynak , Eyal En Gad , Sivagnanam Parthasarathy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A of bit flipping (BF) decoder decodes codewords using a first set of BF thresholds. A first minimum number of iterations of decoding performed on the codewords is determined to achieve a first target decoding rate. Codewords are decoded using a second set of BF thresholds. The first set of BF thresholds are more likely to cause bit flips than the second set of BF thresholds. A second minimum number of iterations of decoding performed on the codewords is determined to achieve a second target decoding rate. Bits in a codeword are flipped using the first set of BF thresholds for the first minimum number of iterations. Bits are flipped in the codeword using the second set of BF thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
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