公开(公告)号：US20240370185A1

公开(公告)日：2024-11-07

申请号：US18774803

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Yoav Weinberg

IPC: G06F3/06

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

公开(公告)号：US20240154625A1

公开(公告)日：2024-05-09

申请号：US18502664

申请日：2023-11-06

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Eyal En Gad ,  Sivagnanam Parthasarathy

IPC: H03M13/11 ,  H03M13/37

CPC classification number: H03M13/1108 ,  H03M13/3746

Abstract: A bit flipping decoder receives a codeword stored in a memory device. The bit flipping decoder determines a plurality of energy function values for the codeword and a least reliable of the energy function values for the codeword. In response to the bit flipping decoder determining the least reliable energy function value fails to satisfy a bit flipping criterion of a current iteration, the bit flipping decoder increments an iteration count. The incrementing of the iteration count bypasses a comparison of the plurality of energy function values with the bit flipping criterion of the current iteration.

公开(公告)号：US20220294473A1

公开(公告)日：2022-09-15

申请号：US17831357

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  G06F11/10

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

公开(公告)号：US20220006473A1

公开(公告)日：2022-01-06

申请号：US17447864

申请日：2021-09-16

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/09 ,  H03M13/29 ,  H03M13/15

Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

公开(公告)号：US20250028373A1

公开(公告)日：2025-01-23

申请号：US18773178

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad ,  Leonid Minz ,  Sivagnanam Parthasarathy

IPC: G06F1/26 ,  G06F11/10

Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.

公开(公告)号：US12164375B2

公开(公告)日：2024-12-10

申请号：US17949655

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad ,  Fan Zhou

IPC: G06F11/10 ,  G06F7/501 ,  G06F11/07 ,  G11C29/44 ,  G11C29/52 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/37 ,  H03M13/45

Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

公开(公告)号：US12014071B2

公开(公告)日：2024-06-18

申请号：US17556080

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/00 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.

公开(公告)号：US20240185898A1

公开(公告)日：2024-06-06

申请号：US18523366

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Leon Zlotnik ,  Yoav Weinberg

IPC: G11C7/10 ,  G06F11/10

CPC classification number: G11C7/1012 ,  G06F11/1068 ,  G11C7/1039

Abstract: A method includes receiving, by shift circuitry, a bit string comprising a plurality of bits and determining, based on a shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry. The method further includes generating a shifted bit string by performing, by the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator and performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.

公开(公告)号：US20240176509A1

公开(公告)日：2024-05-30

申请号：US18521574

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Eyal En Gad ,  Sivagnanam Parthasarathy

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A of bit flipping (BF) decoder decodes codewords using a first set of BF thresholds. A first minimum number of iterations of decoding performed on the codewords is determined to achieve a first target decoding rate. Codewords are decoded using a second set of BF thresholds. The first set of BF thresholds are more likely to cause bit flips than the second set of BF thresholds. A second minimum number of iterations of decoding performed on the codewords is determined to achieve a second target decoding rate. Bits in a codeword are flipped using the first set of BF thresholds for the first minimum number of iterations. Bits are flipped in the codeword using the second set of BF thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.

公开(公告)号：US20210273652A1

公开(公告)日：2021-09-02

申请号：US16806777

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/09

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.