Invention Publication
- Patent Title: INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA
-
Application No.: US18072569Application Date: 2022-11-30
-
Publication No.: US20240178101A1Publication Date: 2024-05-30
- Inventor: Tao CHU , Guowei XU , Feng ZHANG , Chiao-Ti HUANG , Minwoo JANG
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L27/088 ; H01L29/06 ; H01L29/417 ; H01L29/786

Abstract:
Integrated circuit structures having recessed trench contacts and deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. A backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. A conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.
Information query
IPC分类: