公开(公告)号：US20240105770A1

公开(公告)日：2024-03-28

申请号：US17954291

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Tao CHU ,  Guowei XU ,  Chia-Ching LIN ,  Minwoo JANG ,  Feng ZHANG ,  Ting-Hsiang HUNG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L29/778 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. In an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. In an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. In an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.

公开(公告)号：US20250107175A1

公开(公告)日：2025-03-27

申请号：US18372506

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region. Ends of the gate line shared between the NMOS region and the PMOS region are offset from ends of the trench contact structure shared between the NMOS region and the PMOS region.

公开(公告)号：US20240178101A1

公开(公告)日：2024-05-30

申请号：US18072569

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Tao CHU ,  Guowei XU ,  Feng ZHANG ,  Chiao-Ti HUANG ,  Minwoo JANG

IPC: H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/78696

Abstract: Integrated circuit structures having recessed trench contacts and deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. A backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. A conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

公开(公告)号：US20250098260A1

公开(公告)日：2025-03-20

申请号：US18370287

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Guowei XU ,  Feng ZHANG ,  Chiao-Ti HUANG ,  Robin CHAO ,  Tao CHU ,  Chung-Hsun LIN ,  Oleg GOLONZKA ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Anand S. MURTHY

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775

Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

公开(公告)号：US20240178273A1

公开(公告)日：2024-05-30

申请号：US18072559

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Chiao-Ti HUANG ,  Tao CHU ,  Guowei XU ,  Chung-Hsun LIN ,  Brian Greene

IPC: H01L29/06 ,  H01L23/48 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/78696

Abstract: Integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive contact structure is vertically over the epitaxial source or drain structure. The conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. The upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.

公开(公告)号：US20240088292A1

公开(公告)日：2024-03-14

申请号：US17940944

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao CHU ,  Feng ZHANG ,  Minwoo JANG ,  Yanbin LUO ,  Chia-Ching LIN ,  Ting-Hsiang HUNG

IPC: H01L29/78 ,  H01L27/11

CPC classification number: H01L29/7846 ,  H01L27/1104 ,  H01L29/7845 ,  H01L29/785

Abstract: Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.