Invention Publication
- Patent Title: VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYS
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Application No.: US18436365Application Date: 2024-02-08
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Publication No.: US20240179919A1Publication Date: 2024-05-30
- Inventor: Tianhong Yan , Scott Brad Herner , Jie Zhou , Wu-Yi Henry Chien , Eli Harari
- Applicant: SunRise Memory Corporation
- Applicant Address: US CA San Jose
- Assignee: SunRise Memory Corporation
- Current Assignee: SunRise Memory Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H10B43/40
- IPC: H10B43/40 ; H01L21/02 ; H01L21/225 ; H01L21/311 ; H01L21/3205 ; H01L23/528 ; H01L29/45 ; H01L29/66 ; H01L29/786 ; H10B43/10 ; H10B43/27

Abstract:
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
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