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    3-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS
    1.
    发明申请
    3-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS 有权

    公开(公告)号：US20230027837A1

    公开(公告)日：2023-01-26

    申请号：US17812375

    申请日：2022-07-13

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

    IPC: H01L27/1159 ,  H01L27/11597 ,  G11C11/22

    Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

    Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
    2.
    发明授权
    Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array 有权

    公开(公告)号：US11515309B2

    公开(公告)日：2022-11-29

    申请号：US17125477

    申请日：2020-12-17

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Vinod Purayath ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

    IPC: H01L29/66 ,  H01L27/105 ,  H01L29/786 ,  H01L21/3065

    Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

    COOL ELECTRON ERASING IN THIN-FILM STORAGE TRANSISTORS
    5.
    发明申请
    COOL ELECTRON ERASING IN THIN-FILM STORAGE TRANSISTORS 有权

    公开(公告)号：US20210226071A1

    公开(公告)日：2021-07-22

    申请号：US17155673

    申请日：2021-01-22

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

    IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/51

    Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

    Three-dimensional memory string array of thin-film ferroelectric transistors
    7.
    发明授权
    Three-dimensional memory string array of thin-film ferroelectric transistors 有权

    公开(公告)号：US12160996B2

    公开(公告)日：2024-12-03

    申请号：US18483322

    申请日：2023-10-09

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

    IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

    Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

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