Invention Publication
- Patent Title: INTEGRATED NANOSHEET MEMORY ELEMENTS, DEVICES AND METHODS
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Application No.: US18509560Application Date: 2023-11-15
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Publication No.: US20240215220A1Publication Date: 2024-06-27
- Inventor: H. Jim Fulford , Mark I. Gardner
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
A memory element and method of formation is disclosed that includes a transistor integrated with a capacitor through a common nanosheet. The transistor includes a channel, a source region, a drain region and a gate component on at least one side of the channel between the source region and drain region. The channel is formed in a first portion of a nanosheet. The capacitor has a first capacitor component and second capacitor component separated by an insulator. The first capacitor component is provided in a second portion of the nanosheet.
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