公开(公告)号：US12176249B2

公开(公告)日：2024-12-24

申请号：US17667390

申请日：2022-02-08

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Partha Mukhopadhyay

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/786

Abstract: Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.

公开(公告)号：US12133387B2

公开(公告)日：2024-10-29

申请号：US17556943

申请日：2021-12-20

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford ,  Partha Mukhopadhyay

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.

公开(公告)号：US20240215220A1

公开(公告)日：2024-06-27

申请号：US18509560

申请日：2023-11-15

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A memory element and method of formation is disclosed that includes a transistor integrated with a capacitor through a common nanosheet. The transistor includes a channel, a source region, a drain region and a gate component on at least one side of the channel between the source region and drain region. The channel is formed in a first portion of a nanosheet. The capacitor has a first capacitor component and second capacitor component separated by an insulator. The first capacitor component is provided in a second portion of the nanosheet.

公开(公告)号：US12009355B2

公开(公告)日：2024-06-11

申请号：US17574525

申请日：2022-01-12

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Partha Mukhopadhyay

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L27/0207 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/033 ,  H10B12/05 ,  H10B12/31

Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

公开(公告)号：US12001147B2

公开(公告)日：2024-06-04

申请号：US17888553

申请日：2022-08-16

Applicant: Tokyo Electron Limited

Inventor： Daniel J. Fulford ,  Anthony R. Schepis ,  Mark I. Gardner ,  Anton J. Devilliers ,  H. Jim Fulford

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/70633 ,  G03F7/70625

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

公开(公告)号：US20240120375A1

公开(公告)日：2024-04-11

申请号：US17962222

申请日：2022-10-07

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for fabricating and a structure comprising one or more transistors where a transistor includes one or more nanosheets formed based on one or more layers of a nanosheet material. A layer of shell material can at least partly surround the one or more nanosheets to form one or more channels of the transistor. A gate structure of the transistor can at least partly surround each of the one or more channels. The gate structure can include a gate dielectric disposed between the layer of the shell material and a gate metal of the gate structure for each of the nanosheets, where the shell material can include a charge carrier mobility that is greater than a charge carrier mobility of the nanosheet material.

公开(公告)号：US20240063261A1

公开(公告)日：2024-02-22

申请号：US17892890

申请日：2022-08-22

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/306

CPC classification number: H01L29/0673 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/4966 ,  H01L21/28088 ,  H01L21/30604

Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure. A cavity can be formed between the first sidewalls of the plurality of first and second semiconductor channels. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

公开(公告)号：US11887897B2

公开(公告)日：2024-01-30

申请号：US17237628

申请日：2021-04-22

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/417 ,  H01L21/822 ,  H01L29/06

CPC classification number: H01L21/823885 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/41741 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/78642 ,  H01L21/8221 ,  H01L29/0657

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include providing a substrate. The substrate can include a first type region and a second type region. The method can also include forming a multilayer stack on the substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming first and second openings through the multilayer stack to uncover the first and second type regions, respectively. The method can also include forming first and second vertical channel structures within the first and second openings, respectively. Each of the first and second vertical channel structures can have source, gate and drain regions being in contact with vertical sidewalls of the metal layers of the multilayer stack uncovered by a respective one of the first and second openings.

公开(公告)号：US20230402505A1

公开(公告)日：2023-12-14

申请号：US17836904

申请日：2022-06-09

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/66742 ,  H01L27/0688 ,  H01L27/0886

Abstract: A semiconductor device may include a transistor structure. The transistor structure can include a first source/drain structure. The transistor structure can include a first channel structure disposed above the first source/drain structure. The transistor structure can include a second source/drain structure disposed above the first channel structure. A sidewall of a first portion of the first source/drain structure, a sidewall of the first channel structure, and a sidewall of the second source/drain structure can be vertically aligned with one another. The transistor structure can include a first metal electrode disposed around the sidewall of the first channel structure and the sidewall of the second source/drain structure.

公开(公告)号：US11830876B2

公开(公告)日：2023-11-28

申请号：US17451415

申请日：2021-10-19

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Partha Mukhopadhyay

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/7827

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.