A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic causes first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first voltage distribution programmed relative to a first threshold voltage (Vt) level. The control logic causes, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second voltage distribution programmed relative to a second Vt level, wherein the second Vt level is higher than the first Vt level.