- 专利标题: INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS
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申请号: US18621437申请日: 2024-03-29
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公开(公告)号: US20240241645A1公开(公告)日: 2024-07-18
- 发明人: Robert Pawlowski , Shruti Sharma , Fabio Checconi , Sriram Aananthakrishnan , Jesmin Jahan Tithi , Jordi Wolfson-Pou , Joshua B. Fryman
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F3/06
- IPC分类号: G06F3/06
摘要:
Systems, apparatuses and methods may provide for technology that includes a plurality of hash management buffers corresponding to a plurality of pipelines, wherein each hash management buffer in the plurality of hash management buffers is adjacent to a pipeline in the plurality of pipelines, and wherein a first hash management buffer is to issue one or more hash packets associated with one or more hash operations on a hash table. The technology may also include a plurality of hash engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each hash engine in the plurality of hash engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the hash engines is to initialize a target memory destination associated with the hash table and conduct the one or more hash operations in response to the one or more hash packets.
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