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    INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS
    1.
    发明公开
    INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS 审中-公开

    公开(公告)号：US20240241645A1

    公开(公告)日：2024-07-18

    申请号：US18621437

    申请日：2024-03-29

    申请人： Intel Corporation

    发明人： Robert Pawlowski ,  Shruti Sharma ,  Fabio Checconi ,  Sriram Aananthakrishnan ,  Jesmin Jahan Tithi ,  Jordi Wolfson-Pou ,  Joshua B. Fryman

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0673

    摘要： Systems, apparatuses and methods may provide for technology that includes a plurality of hash management buffers corresponding to a plurality of pipelines, wherein each hash management buffer in the plurality of hash management buffers is adjacent to a pipeline in the plurality of pipelines, and wherein a first hash management buffer is to issue one or more hash packets associated with one or more hash operations on a hash table. The technology may also include a plurality of hash engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each hash engine in the plurality of hash engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the hash engines is to initialize a target memory destination associated with the hash table and conduct the one or more hash operations in response to the one or more hash packets.

    INSTRUCTION SET ARCHITECTURE SUPPORT FOR CONDITIONAL DIRECT MEMORY ACCESS DATA MOVEMENT OPERATIONS
    3.
    发明公开
    INSTRUCTION SET ARCHITECTURE SUPPORT FOR CONDITIONAL DIRECT MEMORY ACCESS DATA MOVEMENT OPERATIONS 审中-公开

    公开(公告)号：US20230333998A1

    公开(公告)日：2023-10-19

    申请号：US18312752

    申请日：2023-05-05

    申请人： Intel Corporation

    发明人： Shruti Sharma ,  Robert Pawlowski ,  Fabio Checconi ,  Jesmin Jahan Tithi

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： Systems, apparatuses and methods may provide for technology that includes a plurality of memory engines corresponding to a plurality of pipelines, wherein each memory engine in the plurality of memory engines is adjacent to a pipeline in the plurality of pipelines, and wherein a first memory engine is to request one or more direct memory access (DMA) operations associated with a first pipeline, and a plurality of operation engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each operation engine in the plurality of operation engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the plurality of operation engines is to conduct the one or more DMA operations based on one or more bitmaps.

    TECHNOLOGY TO SUPPORT BITMAP MANIPULATION OPERATIONS USING A DIRECT MEMORY ACCESS INSTRUCTION SET ARCHITECTURE
    5.
    发明公开
    TECHNOLOGY TO SUPPORT BITMAP MANIPULATION OPERATIONS USING A DIRECT MEMORY ACCESS INSTRUCTION SET ARCHITECTURE 审中-公开

    公开(公告)号：US20230315451A1

    公开(公告)日：2023-10-05

    申请号：US18326623

    申请日：2023-05-31

    申请人： Intel Corporation

    发明人： Shruti Sharma ,  Robert Pawlowski ,  Fabio Checconi ,  Jesmin Jahan Tithi

    IPC分类号： G06F9/30 ,  G06F13/28

    CPC分类号： G06F9/30043 ,  G06F9/30079 ,  G06F13/28

    摘要： Systems, apparatuses and methods may provide for technology that detects, by an operation engine, a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) bitmap manipulation request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA bitmap manipulation request, and wherein the first memory engine is to correspond to the first pipeline. The technology also detects, by the operation engine, one or more arguments in the plurality of sub-instruction requests, sends, by the operation engine, one or more load requests to a DRAM in the plurality of DRAMs in accordance with the one or more arguments, and sends, by the operation engine, one or more store requests to the DRAM in accordance with the one or more arguments, wherein the operation engine is to correspond to the DRAM.

    METHODS AND APPARTUS TO CONSTRUCT PROGRAM-DERIVED SEMANTIC GRAPHS
    6.
    发明申请
    METHODS AND APPARTUS TO CONSTRUCT PROGRAM-DERIVED SEMANTIC GRAPHS 有权

    公开(公告)号：US20210117807A1

    公开(公告)日：2021-04-22

    申请号：US17133168

    申请日：2020-12-23

    申请人： Intel Corporation

    发明人： Shengtian Zhou ,  Fangke Ye ,  Roshni G. Iyer ,  Jesmin Jahan Tithi ,  Justin Gottschlich

    IPC分类号： G06N5/00 ,  G06N5/02 ,  G06K9/62 ,  G06F40/00

    摘要： Methods, apparatus, systems and articles of manufacture are disclosed to construct and compare program-derived semantic graphs comprising a leaf node creator to identify a first set of nodes within a parse tree, set a first abstraction level of a program-derived semantic graph (PSG) to contain the first set of nodes, an abstraction level determiner to access a second set of nodes, the second set of nodes to include the set of nodes in the PSG, create a third set of nodes, the third set of nodes to include the set of possible nodes at an abstraction level, determine whether the abstraction level is deterministic, a rule-based abstraction level creator to in response to determining the abstraction level is deterministic, construct the abstraction level, and a PSG comparator to access a first PSG and a second PSG, determine if the first PSG and the second PSG satisfy a similarity threshold.

    Methods and apparatus to insert buffers in a dataflow graph
    7.
    发明授权
    Methods and apparatus to insert buffers in a dataflow graph 有权

    公开(公告)号：US10965536B2

    公开(公告)日：2021-03-30

    申请号：US16370934

    申请日：2019-03-30

    申请人： Intel Corporation

    发明人： Kermin E. ChoFleming, Jr. ,  Jesmin Jahan Tithi ,  Suresh Srinivasan ,  Mahesh A. Iyer

    IPC分类号： H04L12/24 ,  H04L12/26 ,  H04L12/861

    摘要： Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.

    INSTRUCTION SET ARCHITECTURE SUPPORT FOR DATA TYPE CONVERSION IN NEAR-MEMORY DMA OPERATIONS
    8.
    发明公开
    INSTRUCTION SET ARCHITECTURE SUPPORT FOR DATA TYPE CONVERSION IN NEAR-MEMORY DMA OPERATIONS 审中-公开

    公开(公告)号：US20240020253A1

    公开(公告)日：2024-01-18

    申请号：US18477787

    申请日：2023-09-29

    申请人： Intel Corporation

    发明人： Shruti Sharma ,  Robert Pawlowski ,  Fabio Checconi ,  Jesmin Jahan Tithi

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  G06F2213/28

    摘要： Systems, apparatuses and methods may provide for technology that detects a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) data type conversion request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA data type conversion request, and wherein the first memory engine is to correspond to the first pipeline, decodes the plurality of sub-instruction requests to identify one or more arguments, loads a source array from a dynamic random access memory (DRAM) in a plurality of DRAMs, wherein the operation engine is to correspond to the DRAM, and conducts a conversion of the source array from a first data type to a second data type in accordance with the one or more arguments.

    METHODS AND APPARATUS TO DETERMINE EXECUTION COST
    9.
    发明申请
    METHODS AND APPARATUS TO DETERMINE EXECUTION COST 有权

    公开(公告)号：US20220091895A1

    公开(公告)日：2022-03-24

    申请号：US17541016

    申请日：2021-12-02

    申请人： Intel Corporation

    发明人： Niranjan Hasabnis ,  Justin Gottschlich ,  Jesmin Jahan Tithi ,  Anand Venkat

    IPC分类号： G06F9/50 ,  G06F9/30 ,  G06F9/455 ,  G06F9/38

    摘要： Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.