Invention Publication
- Patent Title: MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF
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Application No.: US18633866Application Date: 2024-04-12
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Publication No.: US20240258234A1Publication Date: 2024-08-01
- Inventor: Kosuke YANAGIDAIRA , Chikaaki KODAMA
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: KIOXIA CORPORATION
- Current Assignee: KIOXIA CORPORATION
- Current Assignee Address: JP Tokyo
- Priority: JP 07320444 2007.12.12
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/311 ; H01L21/768 ; H01L23/48 ; H01L23/522 ; H01L27/02 ; H10B41/10 ; H10B41/40 ; H10B41/41

Abstract:
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
Information query
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