Invention Publication
- Patent Title: FIN CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
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Application No.: US18633037Application Date: 2024-04-11
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Publication No.: US20240276698A1Publication Date: 2024-08-15
- Inventor: Tahir GHANI , Byron HO , Curtis W. WARD , Michael L. HATTENDORF , Christopher P. AUTH
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- The original application number of the division: US15859327 2017.12.29
- Main IPC: H10B10/00
- IPC: H10B10/00 ; H01L27/06 ; H01L27/092 ; H01L29/66

Abstract:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
Information query