A power transistor chip package includes a power transistor chip having a first load electrode on a first side, a second load electrode on a second (opposite) side, and a control electrode. The power transistor chip is disposed on a chip pad, with the first side facing the pad and the first load electrode electrically connected to the pad. An encapsulation body encapsulates the power transistor chip and includes a footprint side, a top (opposite) side, and side faces extending between the footprint and top sides. A first package load terminal is electrically connected to the first load electrode. Part I and part II second package load terminals are both electrically connected directly to the second load electrode. A package control terminal is electrically connected to the control electrode. The part I and part II second package load terminals are aligned with opposite sides faces of the encapsulation body.