The disclosed technology generally relates to a complementary field effect transistor (CFET) cell. In one aspect, the CFET cell includes: a first transistor structure arranged in a first tier of the CFET cell; a second transistor structure arranged in a second tier of the CFET cell above the first tier; a set of top signal routing lines formed in a first metal layer above the second tier and connected to the first and the second transistor structures from above; and at least one bottom signal routing line formed in a second metal layer below the first tier and connected to the first transistor structure from below. The disclosed technology also generally relates to a method of fabricating a CFET cell.