A semiconductor structure with a nanosheet device region with GAA nanosheet FETs on a bottom dielectric isolation layer. The GAA nanosheet FETs connect by a frontside contact to the frontside back-end-of-line (BEOL) interconnect wiring and by a backside contact to the backside BEOL interconnect wiring. The semiconductor structure includes a finFET device region with one or more finFET devices on bottom interlayer dielectric material. The finFET devices with a thick gate oxide connect by a frontside contact to the frontside BEOL interconnect wiring. The semiconductor structure also includes a three-dimensional MIM capacitor region with one or more three-dimensional MIM capacitors. The three-dimensional MIM capacitors with a high capacitance have a fin-like backside metal plate covered by a high-k dielectric material or super capacitor materials that is under a frontside metal plate. The three-dimensional MIM capacitors connect to the frontside BEOL interconnect wiring and the backside BEOL interconnect wiring.