A memory device and a manufacturing method thereof are provided. The memory device includes: active regions, defined in a semiconductor substrate; word line structures, formed on the semiconductor substrate, and intersected with the active regions, wherein each of the word line structures includes a floating gate and a control gate stacked on the floating gate; first protection layers, respectively covering an upper part of the control gate in one of the word line structures, wherein a bottom end of the control gate in each word line structure is lower than a bottom end of each first protection layer; and a second protection layer, covering the first protection layers, and wrapping the word line structures.