公开(公告)号：US12119261B2

公开(公告)日：2024-10-15

申请号：US17712461

申请日：2022-04-04

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hung Lin ,  Kao-Tsair Tsai ,  Chung-Hsien Liu ,  Tz-Hau Guo ,  Yen-Jui Chu

IPC: H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823475

Abstract: A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.

公开(公告)号：US12176440B2

公开(公告)日：2024-12-24

申请号：US17518270

申请日：2021-11-03

Applicant: Winbond Electronics Corp.

Inventor： Shang-Rong Wu ,  Ming-Che Lin ,  Chung-Hsien Liu

IPC: H01L21/764 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method of forming the semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

公开(公告)号：US20190319037A1

公开(公告)日：2019-10-17

申请号：US16215666

申请日：2018-12-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L27/11531

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

公开(公告)号：US10381449B2

公开(公告)日：2019-08-13

申请号：US15867736

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L21/311 ,  H01L29/49 ,  H01L27/11521 ,  H01L21/762

Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

公开(公告)号：US10566337B2

公开(公告)日：2020-02-18

申请号：US16215666

申请日：2018-12-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L27/11531 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/11541 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/28

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

公开(公告)号：US20190341449A1

公开(公告)日：2019-11-07

申请号：US16516242

申请日：2019-07-18

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/11517 ,  H01L21/28 ,  H01L27/11521

Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.

公开(公告)号：US20180308929A1

公开(公告)日：2018-10-25

申请号：US15690298

申请日：2017-08-30

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L29/06 ,  H01L27/11517 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/7881

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

公开(公告)号：US20240349499A1

公开(公告)日：2024-10-17

申请号：US18342713

申请日：2023-06-27

Applicant: Winbond Electronics Corp.

Inventor： Tzu-Yun Huang ,  Chung-Hsien Liu

IPC: H10B41/35 ,  H01L29/423 ,  H10B41/10

CPC classification number: H10B41/35 ,  H01L29/42324 ,  H10B41/10

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes: active regions, defined in a semiconductor substrate; word line structures, formed on the semiconductor substrate, and intersected with the active regions, wherein each of the word line structures includes a floating gate and a control gate stacked on the floating gate; first protection layers, respectively covering an upper part of the control gate in one of the word line structures, wherein a bottom end of the control gate in each word line structure is lower than a bottom end of each first protection layer; and a second protection layer, covering the first protection layers, and wrapping the word line structures.

公开(公告)号：US10418440B2

公开(公告)日：2019-09-17

申请号：US15690298

申请日：2017-08-30

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L21/02 ,  H01L21/336 ,  H01L29/06 ,  H01L27/11517 ,  H01L21/762 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

公开(公告)号：US20190088486A1

公开(公告)日：2019-03-21

申请号：US16112780

申请日：2018-08-27

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L21/28 ,  H01L21/762 ,  H01L27/11521 ,  H01L21/02 ,  H01L29/423

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first conductive layer, a first oxide layer, and a hardmask layer are sequentially formed on a substrate. The hardmask layer and the first oxide layer are patterned to form a stacking structure including a hardmask pattern and a first oxide pattern. An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer, and a region of the first conductive layer adjacent to a sidewall of the stacking structure are oxidized to form an extending oxide pattern. The second oxide layer is removed. The stacking structure is applied as a mask to remove an exposed portion of the first conductive layer and the substrate therebelow, such that a first conductive structure and a recess in the substrate are formed. The stacking structure is removed. The extending oxide pattern is removed.