Invention Publication
- Patent Title: METHODS OF DICING WAFERS HAVING ARRAYS OF SEMICONDUCTOR CHIPS THEREIN AND SEMICONDUCTOR CHIPS FORMED THEREBY
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Application No.: US18636463Application Date: 2024-04-16
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Publication No.: US20240355678A1Publication Date: 2024-10-24
- Inventor: Junho Yoon , Junyun Kweon , Haemin Park , Kwangyong Lee , Jesung Kim , Dayoung Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR 20230051431 2023.04.19 KR 20230092476 2023.07.17
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/00

Abstract:
A semiconductor chip includes an active layer on a top surface of an underlying base substrate. The active layer has: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers. A protective layer is also provided, which covers at least a portion of a top surface of the active layer. A vertical level of a bottom of the chamfered edge may be higher than a vertical level of the top surface of the base substrate.
Information query
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