公开(公告)号：US20240355678A1

公开(公告)日：2024-10-24

申请号：US18636463

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Junyun Kweon ,  Haemin Park ,  Kwangyong Lee ,  Jesung Kim ,  Dayoung Cho

IPC: H01L21/78 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor chip includes an active layer on a top surface of an underlying base substrate. The active layer has: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers. A protective layer is also provided, which covers at least a portion of a top surface of the active layer. A vertical level of a bottom of the chamfered edge may be higher than a vertical level of the top surface of the base substrate.

公开(公告)号：US20240178000A1

公开(公告)日：2024-05-30

申请号：US18519501

申请日：2023-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jesung Kim ,  Haemin Park ,  Heejae Nam ,  Junggeun Shin ,  Junho Yoon ,  Jungho Choi

IPC: H01L21/304 ,  B23K26/53 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/3043 ,  B23K26/53 ,  H01L21/6836 ,  H01L21/78 ,  B23K2101/40 ,  H01L2221/68327

Abstract: A wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks.