An integrated semiconductor device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area greater than 1,000 mm2.