A semiconductor package may include a semiconductor chip having a first surface and a second surface opposite to the first surface and having a plurality of circuit patterns provided in the second surface, a redistribution wiring layer on the second surface of the semiconductor chip and having a plurality of redistribution wirings and a plurality of bonding pads, the redistribution wirings being electrically connected to the circuit patterns, the bonding pads electrically connected to the redistribution wirings and exposed from a lower surface, a plurality of conductive bumps on the plurality of bonding pads, respectively, and a plurality of spacers on the lower surface of the redistribution wiring layer and configured to align the plurality of conductive bumps through respective through holes of a test socket and to space the redistribution wiring layer from the test socket.