公开(公告)号：US12237285B2

公开(公告)日：2025-02-25

申请号：US18236545

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gayoung Kim ,  Hyungsun Jang

IPC: H01L23/00

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

公开(公告)号：US11967578B2

公开(公告)日：2024-04-23

申请号：US17479042

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekul Lee ,  Hyungsun Jang ,  Gayoung Kim ,  Minjeong Shin

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/73101 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating laver, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The lost has a ring shape having an inner surface and an outer surface when viewed a top view. A maximum width of the inner surface is less than a Maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.

公开(公告)号：US11557560B2

公开(公告)日：2023-01-17

申请号：US17223601

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeohoon Yoon ,  Hyungsun Jang

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.

公开(公告)号：US20240142493A1

公开(公告)日：2024-05-02

申请号：US18497401

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Han ,  Jaekul Lee ,  Hyungsun Jang ,  Taehun Kim

IPC: G01R1/04 ,  G01R31/28 ,  H01L23/00

CPC classification number: G01R1/0466 ,  G01R31/2863 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/13006 ,  H01L2224/29022

Abstract: A socket for testing a semiconductor package includes a body having an internal space configured to accommodate a semiconductor package; and at least a first spacer on the body and positioned to contact a first surface of the semiconductor package when the semiconductor package is placed on the body. The body includes a lower socket portion provided with through-holes, configured through which to receive meter reading pins that contact external connection terminals of the semiconductor package, and an upper socket portion disposed above the lower socket portion, and the first spacer is disposed on a surface of the lower socket portion that faces the first surface of the semiconductor package when the semiconductor package is placed on the body.

公开(公告)号：US11769743B2

公开(公告)日：2023-09-26

申请号：US17468008

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gayoung Kim ,  Hyungsun Jang

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05557 ,  H01L2224/08059 ,  H01L2224/13021 ,  H01L2924/35121

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

公开(公告)号：US20220246563A1

公开(公告)日：2022-08-04

申请号：US17468008

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gayoung Kim ,  Hyungsun Jang

IPC: H01L23/00

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

公开(公告)号：US20250105187A1

公开(公告)日：2025-03-27

申请号：US18976121

申请日：2024-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gayoung Kim ,  Hyungsun Jang

IPC: H01L23/00

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

公开(公告)号：US12205913B2

公开(公告)日：2025-01-21

申请号：US18236545

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gayoung Kim ,  Hyungsun Jang

IPC: H01L23/00

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

公开(公告)号：US20230395548A1

公开(公告)日：2023-12-07

申请号：US18236545

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gayoung Kim ,  Hyungsun Jang

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/08059 ,  H01L2924/35121 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13021 ,  H01L2224/05557

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

公开(公告)号：US20240395747A1

公开(公告)日：2024-11-28

申请号：US18638757

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekul Lee ,  Hyungsun Jang ,  Sanguk Han ,  Taehun Kim

IPC: H01L23/00

Abstract: A semiconductor package may include a semiconductor chip having a first surface and a second surface opposite to the first surface and having a plurality of circuit patterns provided in the second surface, a redistribution wiring layer on the second surface of the semiconductor chip and having a plurality of redistribution wirings and a plurality of bonding pads, the redistribution wirings being electrically connected to the circuit patterns, the bonding pads electrically connected to the redistribution wirings and exposed from a lower surface, a plurality of conductive bumps on the plurality of bonding pads, respectively, and a plurality of spacers on the lower surface of the redistribution wiring layer and configured to align the plurality of conductive bumps through respective through holes of a test socket and to space the redistribution wiring layer from the test socket.