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公开(公告)号:US20230297832A1
公开(公告)日:2023-09-21
申请号:US18201405
申请日:2023-05-24
发明人: Eunkyu OH , Taehun Kim , Minsoo Kim , Yunhu Ji , Sushill Khyalla
IPC分类号: G06N3/08 , G06N3/0455
CPC分类号: G06N3/08 , G06N3/0455
摘要: An electronic device is provided. The electronic device includes: a memory storing a neural network model; and a processor configured to: obtain a plurality of individual graphs based on an access history for a plurality of contents over a plurality of sessions; generate an integrated graph, in which the plurality of individual graphs are integrated, based on a connection relationship between nodes included in the plurality of individual graphs and a number of times each connection between the nodes is repeated; obtain a plurality of augmented graphs by augmenting each of the plurality of individual graphs based on the integrated graph; and train the neural network model to provide recommended content based on the plurality of augmented graphs.
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公开(公告)号:US20230163088A1
公开(公告)日:2023-05-25
申请号:US18151622
申请日:2023-01-09
发明人: Hyuekjae Lee , Jongho Lee , Jihoon Kim , Taehun Kim , Sangcheon Park , Jinkyeong Seol , Sanghoon Lee
IPC分类号: H01L23/00 , H01L25/065 , H01L25/18 , H01L21/56 , H01L25/00
CPC分类号: H01L24/06 , H01L25/0652 , H01L25/18 , H01L24/08 , H01L24/32 , H01L24/05 , H01L24/13 , H01L25/0655 , H01L21/561 , H01L25/50 , H01L24/94 , H01L24/96 , H01L24/92 , H01L25/0657 , H01L2224/83099 , H01L2225/06541 , H01L2225/06548 , H01L2224/32145 , H01L2224/08148 , H01L2224/08145 , H01L2224/05073 , H01L2224/05025 , H01L2224/05564 , H01L2224/05562 , H01L2224/08121 , H01L2224/06182 , H01L2224/13024 , H01L2224/08225 , H01L2224/32225 , H01L2224/92142 , H01L2224/8389 , H01L2224/80895
摘要: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.
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公开(公告)号:US11658148B2
公开(公告)日:2023-05-23
申请号:US16854452
申请日:2020-04-21
发明人: Hyuekjae Lee , Jihoon Kim , JiHwan Suh , So Youn Lee , Jihwan Hwang , Taehun Kim , Ji-Seok Hong
IPC分类号: H01L25/00 , H01L25/065 , H01L23/00 , H01L25/18 , H01L21/56
CPC分类号: H01L25/0652 , H01L21/565 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L2224/08146 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589
摘要: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.
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公开(公告)号:US11658141B2
公开(公告)日:2023-05-23
申请号:US17680477
申请日:2022-02-25
发明人: Jiseok Hong , Unbyoung Kang , Myungsung Kang , Taehun Kim , Sangcheon Park , Hyuekjae Lee , Jihwan Hwang
CPC分类号: H01L24/08 , H01L22/22 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L23/481 , H01L2224/05124 , H01L2224/05564 , H01L2224/05647 , H01L2224/06051 , H01L2224/08145 , H01L2224/2919 , H01L2224/29028 , H01L2224/32145 , H01L2224/9211
摘要: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
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公开(公告)号:USD971915S1
公开(公告)日:2022-12-06
申请号:US29693761
申请日:2019-06-05
设计人: Chulyong Cho , Byungmin Woo , Jaeneung Lee , Taehun Kim
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公开(公告)号:US11508685B2
公开(公告)日:2022-11-22
申请号:US16992895
申请日:2020-08-13
发明人: Jihwan Suh , Un-Byoung Kang , Taehun Kim , Hyuekjae Lee , Jihwan Hwang , Sang Cheon Park
IPC分类号: H01L23/00 , H01L25/065 , H01L25/18
摘要: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.
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公开(公告)号:US20220181285A1
公开(公告)日:2022-06-09
申请号:US17680477
申请日:2022-02-25
发明人: Jiseok Hong , Unbyoung Kang , Myungsung Kang , Taehun Kim , Sangcheon Park , Hyuekjae Lee , Jihwan Hwang
IPC分类号: H01L23/00 , H01L21/66 , H01L25/065 , H01L25/00
摘要: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
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公开(公告)号:US11309228B2
公开(公告)日:2022-04-19
申请号:US16908128
申请日:2020-06-22
发明人: Sunchul Kim , Taehun Kim , Pyoungwan Kim
IPC分类号: H01L23/367 , H01L23/31 , H01L21/48 , H01L23/373
摘要: A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member.
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公开(公告)号:US20210358875A1
公开(公告)日:2021-11-18
申请号:US17155657
申请日:2021-01-22
发明人: Hyuekjae Lee , Jongho Lee , Jihoon Kim , Taehun Kim , Sangcheon Park , Jinkyeong Seol , Sanghoon Lee
IPC分类号: H01L23/00 , H01L25/065 , H01L25/18 , H01L21/56 , H01L25/00
摘要: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.
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公开(公告)号:US20210104482A1
公开(公告)日:2021-04-08
申请号:US16985445
申请日:2020-08-05
发明人: Jiseok Hong , Unbyoung Kang , Myungsung Kang , Taehun Kim , Sangcheon Park , Hyuekjae Lee , Jihwan Hwang
IPC分类号: H01L23/00 , H01L21/66 , H01L25/00 , H01L25/065
摘要: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
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