Invention Application
- Patent Title: PAGE REQUEST INTERFACE SUPPORT IN HANDLING POINTER FETCH WITH CACHING HOST MEMORY ADDRESS TRANSLATION DATA
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Application No.: US18675476Application Date: 2024-05-28
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Publication No.: US20240411704A1Publication Date: 2024-12-12
- Inventor: Raja V.S. Halaharivi , Prateek Sharma , Sumangal Chakrabarty , Venkat R. Gaddam
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F12/1045
- IPC: G06F12/1045

Abstract:
A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.
Information query
IPC分类: