公开(公告)号：US12298916B2

公开(公告)日：2025-05-13

申请号：US18517370

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Prateek Sharma ,  Raja V. S. Halaharivi ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/123 ,  G06F12/0882

Abstract: A device includes an address translation circuit of host interface circuitry to handle address translation requests to a host system from a host queue interface circuit. The address translation circuit includes cache to store address translations associated with the address translation requests. The host queue interface circuit, coupled to the address translation circuit, is to: pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that missed at the cache; trigger a page request interface (PRI) handler to send a page miss request to a translation agent (TA) of the host, the page miss request including a virtual address of the address translation request; receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the TA; and restart command arbitration on the submission queue that was paused responsive to the restart message.

公开(公告)号：US11789663B2

公开(公告)日：2023-10-17

申请号：US17961716

申请日：2022-10-07

Applicant: Micron Technology, Inc.

Inventor： Venkat R. Gaddam

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0679

Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

公开(公告)号：US11481152B2

公开(公告)日：2022-10-25

申请号：US16992192

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Venkat R. Gaddam

IPC: G06F3/06

Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

公开(公告)号：US20240069807A1

公开(公告)日：2024-02-29

申请号：US17900122

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Venkat R. Gaddam

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.

公开(公告)号：US20230036621A1

公开(公告)日：2023-02-02

申请号：US17961716

申请日：2022-10-07

Applicant: Micron Technology, Inc.

Inventor： Venkat R. Gaddam

IPC: G06F3/06

Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

公开(公告)号：US20240411704A1

公开(公告)日：2024-12-12

申请号：US18675476

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/1045

Abstract: A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

公开(公告)号：US20240411700A1

公开(公告)日：2024-12-12

申请号：US18675486

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/10 ,  G06F12/0802

Abstract: A method includes buffering, in a descriptor queue, descriptors associated with translation units of an LBA-based, direct memory access (DMA) read command of a host system, each descriptor to be linked with a pointer including a physical destination for data associated with a respective translation unit. The method includes sending address translation requests to an address translation circuit for the pointers of respective translation units and detecting an address translation request miss at a cache of the address translation circuit for a first pointer of a first translation unit linked to a first descriptor of the plurality of descriptors. The method includes causing a translation miss message to be sent to a page request interface (PRI) handler, the translation miss message containing a virtual address of the first pointer and to trigger the PRI handler to send a page miss request to a translation agent of the host system.

公开(公告)号：US20240160577A1

公开(公告)日：2024-05-16

申请号：US18505302

申请日：2023-11-09

Applicant: Micron Technology, Inc.

Inventor： Raja V. S. Halaharivi ,  Prateek Sharma ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/1009 ,  G06F12/123

CPC classification number: G06F12/1009 ,  G06F12/123 ,  G06F2212/1021

Abstract: A processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. The address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. A page request interface (PRI) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. The PRI handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. The PRI handler queues the page request groups to be sent to a translation agent of the host system.

公开(公告)号：US20240184710A1

公开(公告)日：2024-06-06

申请号：US18526499

申请日：2023-12-01

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Venkat R. Gaddam

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to modify one or more regions of the memory device; identifying one or more mapping structures associated with each region of the one or more regions of the memory device; determining that a counter satisfies a threshold criterion, wherein the counter indicates a number of memory access commands at the one or more regions; creating a copy of each mapping structure associated with each region; and modifying the copy of each mapping structure according to the request to modify the one or more regions of the memory device.

公开(公告)号：US20240168891A1

公开(公告)日：2024-05-23

申请号：US18517370

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Prateek Sharma ,  Raja V. S. Halaharivi ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/123 ,  G06F12/0882

CPC classification number: G06F12/123 ,  G06F12/0882 ,  G06F2212/1021

Abstract: A device includes an address translation circuit of host interface circuitry to handle address translation requests to a host system from a host queue interface circuit. The address translation circuit includes cache to store address translations associated with the address translation requests. The host queue interface circuit, coupled to the address translation circuit, is to: pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that missed at the cache; trigger a page request interface (PRI) handler to send a page miss request to a translation agent (TA) of the host, the page miss request including a virtual address of the address translation request; receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the TA; and restart command arbitration on the submission queue that was paused responsive to the restart message.