A semiconductor structure includes a first circuit row including one or more first circuit cells and a second circuit row including one or more second circuit cells. At a cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, one or more first gate regions of the one or more first circuit cells in the first circuit row are staggered with one or more second gate regions of the one or more second circuit cells in the second circuit row.