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    STACKED RANDOM-ACCESS-MEMORY WITH COMPLEMENTARY ADJACENT CELLS
    2.
    发明公开
    STACKED RANDOM-ACCESS-MEMORY WITH COMPLEMENTARY ADJACENT CELLS 审中-公开

    公开(公告)号：US20240081037A1

    公开(公告)日：2024-03-07

    申请号：US17930096

    申请日：2022-09-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Brent A. Anderson ,  Albert M. Chu ,  Junli Wang ,  Carl Radens ,  Ruilong Xie

    IPC分类号： H01L27/11 ,  G11C5/06

    CPC分类号： H01L27/1112 ,  G11C5/063

    摘要： A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.

    SRAM WITH BACKSIDE CROSS-COUPLE
    5.
    发明公开
    SRAM WITH BACKSIDE CROSS-COUPLE 审中-公开

    公开(公告)号：US20230345691A1

    公开(公告)日：2023-10-26

    申请号：US17660431

    申请日：2022-04-25

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Ruilong Xie ,  Albert M Chu ,  Carl Radens ,  Kisik Choi

    IPC分类号： H01L27/11 ,  H01L29/417

    CPC分类号： H01L27/1108 ,  H01L29/41733

    摘要： Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

    NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK
    8.
    发明申请
    NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK 有权

    公开(公告)号：US20210359103A1

    公开(公告)日：2021-11-18

    申请号：US16876443

    申请日：2020-05-18

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  JUNTAO LI ,  Dechao Guo ,  Tao Li ,  Tsung-Sheng Kang

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

    摘要： Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.