Invention Application
- Patent Title: MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT
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Application No.: US18338440Application Date: 2023-06-21
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Publication No.: US20240431092A1Publication Date: 2024-12-26
- Inventor: Abhishek A. Sharma , Wilfred Gomes , Tahir Ghani , Anand S. Murthy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.
Information query