Invention Application
- Patent Title: TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY
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Application No.: US18215668Application Date: 2023-06-28
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Publication No.: US20250004983A1Publication Date: 2025-01-02
- Inventor: Brian C. GAIDE , Sneha Bhalchandra DATE , Juan J. NOGUERA SERRA
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Main IPC: G06F15/80
- IPC: G06F15/80

Abstract:
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.
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