Invention Application
- Patent Title: MARGIN TESTER MEASUREMENT USING MACHINE LEARNING
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Application No.: US18769683Application Date: 2024-07-11
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Publication No.: US20250020713A1Publication Date: 2025-01-16
- Inventor: John J. Pickerd , Sam J. Strickling , Kan Tan
- Applicant: Tektronix, Inc.
- Applicant Address: US OR Beaverton
- Assignee: Tektronix, Inc.
- Current Assignee: Tektronix, Inc.
- Current Assignee Address: US OR Beaverton
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A margin tester includes one or more ports to allow the margin tester to connect to a device under test (DUT), a memory, the memory containing a margin tester signature, a transmitter, a receiver to receive signals from the DUT, one or more processors configured to execute code that causes the one or more processors to: receive multiple signals from the receiver through the one or more ports, generate a performance indicator from the multiple signals, send the performance indicator and the margin tester signature to one or more machine learning networks, and receiving a result from the one or more machine learning networks containing a performance measurement prediction for the DUT.
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