An apparatus and method for efficient encoding for trusted environments including full error correction. One embodiment of a processor comprises: a plurality of cores to execute instructions;
a memory controller coupled to the plurality of cores, the memory controller operable in a first error correction mode and a second error correction mode, the memory controller comprising: a decoder to decode first error correction code (ECC) bits encoded in accordance with the first error correction mode to determine a first syndrome and a second syndrome based on data corresponding to the ECC bits; error detection circuitry to determine whether one or both of the first syndrome and the second syndrome indicates an error in the data; and an encoder to generate second ECC bits in accordance with the second error correction mode, the ECC bits to be encoded based on whether one or both of the first syndrome and the second syndrome indicates an error.