公开(公告)号：US20180095812A1

公开(公告)日：2018-04-05

申请号：US15283059

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： SERGEJ DEUTSCH ,  KARANVIR S. GREWAL ,  MICHAEL E. KOUNAVIS

IPC: G06F11/07 ,  H04L9/14 ,  G06F9/455 ,  G06F1/24

CPC classification number: G06F11/079 ,  G06F1/24 ,  G06F9/45558 ,  G06F11/073 ,  G06F11/0751 ,  G06F2009/4557 ,  G06F2009/45591 ,  H04L9/0866 ,  H04L9/14 ,  H04L9/3226

Abstract: Methods, apparatus, and system to analyze a memory integrity violation and determine whether its cause was hardware or software based.

公开(公告)号：US20190220349A1

公开(公告)日：2019-07-18

申请号：US16368430

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： SERGEJ DEUTSCH ,  WEI WU ,  DAVID M. DURHAM ,  KARANVIR GREWAL

IPC: G06F11/10 ,  H04L9/32

Abstract: In one example a computer implemented method comprises generating an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits, applying a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits, generating a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits, encoding the first plurality of data blocks and the metadata block to generate a first encoded data set, and providing the encoded data set and the encoded metadata block for storage on a memory module. Other examples may be described.

公开(公告)号：US20180181337A1

公开(公告)日：2018-06-28

申请号：US15390359

申请日：2016-12-23

Applicant: INTEL CORPORATION

Inventor： DAVID M. DURHAM ,  SERGEJ DEUTSCH ,  SAEEDEH KOMIJANI ,  ALPA T. NARENDRA TRIVEDI ,  SIDDHARTHA CHHABRA

IPC: G06F3/06

CPC classification number: G06F9/30047 ,  G06F21/79 ,  H03M7/30 ,  H03M7/6064

Abstract: Techniques and computing devices for compression memory coloring are described. In one embodiment, for example, an apparatus may include at least one memory, at least on processor, and logic for compression memory coloring, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to determine whether data to be written to memory is compressible, generate a compressed data element responsive to determining data is compressible, the data element comprising a compression indicator, a color, and compressed data, and write the compressed data element to memory. Other embodiments are described and claimed.

公开(公告)号：US20180074975A1

公开(公告)日：2018-03-15

申请号：US15263962

申请日：2016-09-13

Applicant: Intel Corporation

Inventor： SERGEJ DEUTSCH ,  DAVID M. DURHAM ,  KARANVIR S. GREWAL ,  MICHAEL E. KOUNAVIS

IPC: G06F12/14 ,  H04L9/06 ,  G06F21/72 ,  G06F21/79 ,  G06F3/06 ,  G06F13/28

CPC classification number: G06F12/1408 ,  G06F3/0619 ,  G06F3/0623 ,  G06F3/065 ,  G06F3/0673 ,  G06F13/28 ,  G06F21/72 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/0631 ,  H04L9/0637 ,  H04L2209/12

Abstract: Embodiments of apparatus, method, and storage medium associated with multi-stage memory integrity for securing/protecting memory content are described herein. In some embodiments, an apparatus may include multiple stages having respective encryption engines to encrypt data in response to a write or restore operation; wherein the encryption engines are to successively encrypt the data in a plurality of encryption stages using a plurality of tweaks based on a plurality of selectors of different types {s1, s2, . . . }. In embodiments, the multiple stages may further comprise one or more decryption engines to partially, fully, or pseudo decrypt the plural encrypted data, in response to a read, move or copy operation; wherein the one or more decryption engines are to partially, fully, or pseudo decrypt the plural encrypted data in one or more decryption stages using one or more tweaks based on a subset of the selectors of different types {s1, s2, . . . }.

公开(公告)号：US20250103428A1

公开(公告)日：2025-03-27

申请号：US18373780

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： SERGEJ DEUTSCH ,  KARANVIR GREWAL ,  DAVID M. DURHAM

IPC: G06F11/10 ,  G06F21/64

Abstract: An apparatus and method for efficient encoding for trusted environments including full error correction. One embodiment of a processor comprises: a plurality of cores to execute instructions;
a memory controller coupled to the plurality of cores, the memory controller operable in a first error correction mode and a second error correction mode, the memory controller comprising: a decoder to decode first error correction code (ECC) bits encoded in accordance with the first error correction mode to determine a first syndrome and a second syndrome based on data corresponding to the ECC bits; error detection circuitry to determine whether one or both of the first syndrome and the second syndrome indicates an error in the data; and an encoder to generate second ECC bits in accordance with the second error correction mode, the ECC bits to be encoded based on whether one or both of the first syndrome and the second syndrome indicates an error.