Invention Application
- Patent Title: DIE-TO-DIE INPUT/OUTPUT SIGNAL ROUTING UTILIZING OPPOSING DIE SURFACES IN INTEGRATED CIRCUIT COMPONENT PACKAGING
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Application No.: US18478950Application Date: 2023-09-29
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Publication No.: US20250112205A1Publication Date: 2025-04-03
- Inventor: Prashant Majhi , Nitin A. Deshpande , Omkar G. Karhade , Surhud V. Khare
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/56 ; H01L23/00 ; H01L23/538 ; H01L25/00

Abstract:
Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. Embedded bridges or chiplets or not used for die-to-die I/O routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.
Public/Granted literature
- US2711020A Cheese cutting apparatus Public/Granted day:1955-06-21
Information query
IPC分类: