公开(公告)号：US20250112205A1

公开(公告)日：2025-04-03

申请号：US18478950

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  Surhud V. Khare

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. Embedded bridges or chiplets or not used for die-to-die I/O routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.

公开(公告)号：US20240222347A1

公开(公告)日：2024-07-04

申请号：US18148338

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Kuljit S. Bains ,  Wilfred Gomes ,  Don Douglas Josephson ,  Surhud V. Khare ,  Christopher Philip Mozak ,  Randy B. Osborne ,  Pushkar Ranade ,  Abhishek Anil Sharma

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).