A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is wrapped on a sidewall of an active area of each GAA transistor of the second set. Additional devices and methods are disclosed.