A memory device is provided. The memory device includes: a memory cell array implemented in a first chip; and a peripheral circuit implemented in a second chip and a third chip which overlaps the first chip along a vertical direction. The peripheral circuit includes: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and including at least one low-voltage transistor. The first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and including at least one low-voltage transistor.