A program-controlled data-processing system in which ''''threecycle overlap'''' execution of program instructions is employed. The processor comprises three circuit arrangements which are concurrently operative with respect to three successive program order words. Each order word which is executed by the control arrangement is first brought into one circuit arrangement (the Buffer Order Word Register) and at a discrete time thereafter each instruction is moved to a second circuit arrangement (the Order Word Register). While the order word is in the Buffer Order Word Register, the instruction portion of the order word is decoded by a corresponding decoder circuit (the Buffer Order Word Decoder) and while it resides in the Order Word Register the instruction portion of the order word is decoded by a second decoder, namely, the Order Word Decoder. The third circuit arrangement serves to transmit commands to the program store to obtain a next succeeding order word from the Buffer Order Word Register.