Program controlled data processing system
    2.
    发明授权
    Program controlled data processing system 失效
    程序控制数据处理系统

    公开(公告)号:US3651480A

    公开(公告)日:1972-03-21

    申请号:US3651480D

    申请日:1967-11-24

    IPC分类号: G06F11/16 H04Q3/545 G06F15/16

    摘要: A program controlled data processor system which employs functionally equivalent first and second control units on a mutually exclusive basis to control an input-output system. The processor system comprises a plurality of independent memory units and communication between the control means and the independent memory units is by way of communication paths which may be selectively associated with any of the memory units and with either of the control means. The processor arrangement includes means for insuring that the two control means simultaneously carry out identical work functions.

    摘要翻译: 一种程序控制的数据处理器系统,其在相互排斥的基础上采用功能上等效的第一和第二控制单元来控制输入 - 输出系统。 处理器系统包括多个独立的存储器单元,并且控制装置和独立存储器单元之间的通信是通过可以选择性地与任何存储器单元和控制装置中的任何一个相关联的通信路径。 处理器装置包括用于确保两个控制装置同时执行相同功能的装置。

    Cooperative processor control of communication switching office
    4.
    发明授权
    Cooperative processor control of communication switching office 失效
    通信交换机构合作处理器控制

    公开(公告)号:US3643032A

    公开(公告)日:1972-02-15

    申请号:US3643032D

    申请日:1969-09-19

    IPC分类号: H04M3/00 H04Q3/545 H04Q3/54

    CPC分类号: H04Q3/5455

    摘要: A communications switching office in which each of a plurality of separate processors independently hunts idle paths between terminals of an associated network and in which two separate processors cooperatively hunt idle paths between terminals of the two associated networks by means of data messages exchanged between the two processors. A data transmission arrangement is provided between the processors and internetwork junctors provide connections between the networks.

    摘要翻译: 一种通信交换局,其中多个单独的处理器中的每一个独立地在相关联的网络的终端之间寻找空闲路径,并且其中两个单独的处理器借助于两个处理器之间交换的数据消息协作地在两个相关联的网络的终端之间寻找空闲路径 。 在处理器之间提供数据传输布置,并且互连网络旁路器提供网络之间的连接。

    Program-controlled data-processing system
    5.
    发明授权
    Program-controlled data-processing system 失效
    程序控制数据处理系统

    公开(公告)号:US3623008A

    公开(公告)日:1971-11-23

    申请号:US3623008D

    申请日:1967-11-24

    IPC分类号: G06F9/38 H04Q3/545 G06F9/06

    摘要: A program-controlled data-processing system in which ''''threecycle overlap'''' execution of program instructions is employed. The processor comprises three circuit arrangements which are concurrently operative with respect to three successive program order words. Each order word which is executed by the control arrangement is first brought into one circuit arrangement (the Buffer Order Word Register) and at a discrete time thereafter each instruction is moved to a second circuit arrangement (the Order Word Register). While the order word is in the Buffer Order Word Register, the instruction portion of the order word is decoded by a corresponding decoder circuit (the Buffer Order Word Decoder) and while it resides in the Order Word Register the instruction portion of the order word is decoded by a second decoder, namely, the Order Word Decoder. The third circuit arrangement serves to transmit commands to the program store to obtain a next succeeding order word from the Buffer Order Word Register.

    Program controlled data processing system
    7.
    发明授权
    Program controlled data processing system 失效
    程序控制数据处理系统

    公开(公告)号:US3568157A

    公开(公告)日:1971-03-02

    申请号:US3568157D

    申请日:1967-11-24

    摘要: A program controlled telephone switching system is shown as an example of a real time program controlled data processing system. The system work functions of the telephone switching system are performed at assigned levels of a priority hierarchy. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs, which require a fair degree of timing precision, are performed and a plurality of trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The telephone functions which are performed at the base level are allocated processor time in accordance with a base level executive program frequency table. The base level executive program provides time for execution of certain low priority maintenance functions. In the absence of trouble the processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupt programs are initiated upon the detection of corresponding classes of trouble.