A bus assigner in an electronic data processing system for selectively assigning access to a system bus to one of a plurality of microprocessors comprising a multiprocessing system. In an embodiment of the present invention, logic circuitry is provided for assigning a priority of operation to each of the microprocessors, each microprocessor having a different assigned priority. The bus assigner selectively assigns access to the sysstem bus to the microprocessor having the highest priority whenever one or more of the microprocessors requests access to the system bus. In an alternative embodiment, the bus assigner sequentially scans the microprocessors for requests for access to the system bus and assigns access to the system bus in the order in which the requests are received by the bus assigner as it scans the microprocessors.