A matrix circuit acting as a read only memory (ROM) comprises first and second groups of input lines, a third group of input lines arranged between the first and second groups of input lines, a plurality of groups of output lines intersecting the input lines off the first, second and third group, each group of the output lines having one terminal commonly connected in a wired OR fasion to one end of a power source and having the other terminal commonly connected to the ground. A plurality of first switching elements are respectively connected to the output lines and selectively driven by an input signal supplied to the first group of the input lines, a plurality of second switching elements driven by the same input signal as that supplied to the first switching elements and respectively connected to the output lines each lying adjacent to the output lines connected with the first switching elements, and a plurality of third switching elements respectively connected between the adjacent output lines and selectively driven by an input signal supplied to the third group of input lines.