发明授权
US4121166A Phase synchronizing circuit for demodulation of multi-phase PSK signals
失效
用于解调多相PSK信号的相位同步电路
- 专利标题: Phase synchronizing circuit for demodulation of multi-phase PSK signals
- 专利标题(中): 用于解调多相PSK信号的相位同步电路
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申请号: US850518申请日: 1977-11-11
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公开(公告)号: US4121166A公开(公告)日: 1978-10-17
- 发明人: Youichi Matsumoto , Yoshimi Tagashira
- 申请人: Youichi Matsumoto , Yoshimi Tagashira
- 申请人地址: JPX Tokyo
- 专利权人: Nippon Electric Co., Ltd.
- 当前专利权人: Nippon Electric Co., Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX51-136044 19761111
- 主分类号: H03L7/10
- IPC分类号: H03L7/10 ; H03L7/12 ; H04L27/227 ; H03D3/02
摘要:
A phase synchronizing circuit for the demodulation of multi-phase PSK signals has a broadened capture frequency range while avoiding false capture. The circuit includes a phase synchronizing loop having a voltage controlled oscillator for generating a variable frequency output in response to a control voltage and a phase comparator for providing a comparison output representative of the phase difference between the output of the voltage controlled oscillator and an input signal. The comparison output serves as the control voltage for the voltage controlled oscillator. A phase-lock detection circuit is connected to the phase synchronizing loop to detect the phase-synchronized or unsynchronized states of the loop. A low frequency sweep generator is responsive to the phase-lock detection circuit for generating a variable-amplitude voltage which is supplied as a frequency sweep voltage to the voltage controlled oscillator. The frequency sweep voltage is provided for a period of time running from the detection by phase-lock detection circuit of the phase unsynchronized state to a predetermined period of time after the detection of the change from the phase unsynchronized state to the synchronized state.
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