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US4364076A Co-planar well-type charge coupled device with enhanced storage capacity and reduced leakage current 失效
共平面阱型电荷耦合器件具有增强的存储容量和减少的漏电流

Co-planar well-type charge coupled device with enhanced storage capacity
and reduced leakage current
Abstract:
A charge coupled device memory is disclosed which includes a plurality of stages having increased charged storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under the phase electrodes is divided into barrier regions and adjacent well regions bounded by the channel. A dopant layer of a second-type conductivity lies in each of the well regions relatively near to the first surface. An enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions relatively far from the surface having a doping which is greater than the doping of the first-type conductivity semiconductor substrate.
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