A phase-locked loop circuit comprising a reference oscillator (1), a reference frequency divider (2) for dividing the output signal of the reference oscillator, a programmable frequency divider (3), a phase comparator (4) for monitoring the difference in phase between the output signal of the two frequency dividers, a lock detector (11) for generating a first signal which is pulse-shaped or rectangular when the above-mentioned difference in phase is generated, and a digital signal maintaining circuit (100) for converting the first signal into a second directed current signal.